Calculating machines



May 17, 1960 Filed Jan. 30, 1956 G. B. GREENE 2,936,957

CALCULATING MACHINES 3 Sheets-Sheet 1 .D 53 V59 E 0 I lE E 5/ /30 B2 6mmvm.

eor'ye B. Greene. IE lE E BY 44444 MAW y 1960 G. B. GREENE 2,936,957

CALCULATING MACHINES Filed Jan. so, 1956 Y 3 Sheets-Sheet 2 M E flaw 53Li A i1- 5 4 /3//@--|)FI ar /12 IN VEN TOR. 6 earge B. Gre e/ze BY May17, 1960 G. B. GREENE CALCULATING mcmmzs 3 Sheets-Sheet 3 Filed Jan. 30,1956 IN V EN TOR.

George .5. ree/ze.

George B. Greene,-

;:, Other. objects of the invention will 2,936,957 CALCULATING MACHINESBerkeley, Calif., as'signor to Smith- Corona Mai-chant Inc., acorporation of NewYork Application January 30, 19 56, No. 562,272 6Claims. c1. 2 3 167) for use in such with arithmetic now Patent No.2,922,144, and a simple control system.

The magnetic discrecirculation memories receive and store multidigitbinary numbers, hereinafter called words, and subsequently perform, inconjunction with the other basic elements, arithmetic operations using"the stored words as operands.{ One of the recirculation memories isemployed for-registering on its magnetic storage disc the result of thearithmetic operation.

It is therefore a primary object of this invention to pro vide animproved arithmetic unit.

Other objects are: 7

To provide an improved adding circuit;

To provide an improved subtracting circuit;

To provide an improved multiplying circuit; V

To' provide an arithmetic unit oflow cost and of compact construction;

To incorporate small-size, low-cost, magnetic disc recirculationmemories into an arithmetic unit;

'To provide an accumulator comprising a recirculation .memory and asingle trigger circuit;

To store each of a plurality of arithmetic operands in a respectiverecirculation memory; to combine said operands according to amanually-selected rule of arithmetic operation; and to store theresultof such arithmetic operation in a'recirculation memoryyand Tomanually control the arithmetic combination ofa plurality of operands,each stored in a respectiverecirc'ulationmemory, and to store the resultof-such arithmetic combination in a recirculation memory.

accompanying drawings, whereini 'Fig. 5 is the schematic diagram of atypical delay line; Fig. 6- is a block representation of a recirculationmeme 'ory as used inthe'present invention; I

Fig. 7 is'an illustration of; a recirculation memory showing'the readingand writing transducers and the rotating discwi th its magnetic memoryisland;

,Fig- 8 is a schematic diagram of a recirculation memory as employed inthe present invention; and

appear from the following description in which reference is made to theFig. l'is a schematic diagram of a typical trigger cir- V from the fact"the f0; side, and the trigger is said to be Phtented May 17, .1960

Fig. 9. is a block diagram of a pr rerred;embpciimeat of 'an arithmeticunit for performing addition, subtraction, and multiplication in thebinary system.

A detailed descrlptron of the operation of the arithmetic unit as itperforms binary addition, subtractiomjand multiplication will be givenfollowing descriptions fof "the? various circuit elements which "areemplo ed in the present invention.

CIRCUIT ELEMENTS form, such a trigger circuit comprises a pair of triodevacuum tubes having a bias arrangement common to both tubes, and havinggrid-to-anod'e resistive cross-coupling. The value'of a triggercircuitdei'ives that the circuit has two stable states of equilibrium,viz: when either tube is conducting and the other tubeis cut off. Thecircuit may be caused to trigger abduptly from onestable state to theother, by the application of proper control potentials to one or moreelectrodes. Inyeach state of circuit equilibrium,

thereis a respective stable set of circuit currents; thereeach tubethere are two possible fore, at the anode of potential levels, namely,arel'atively low potential if a tube is conducting and arelativelyhighpotential when 7 In the present invention, this difiercircuits. r

A modified Eccles-Jordan trigger circuit, as employed in 7 thisinvention, is shownas T. in Fig. Since the trigger circuit is atwo-state device and 1s used .a s ,-an velement in'a binary arithmeticorgan, it is convenient to distinguish the two stable representations.Thus, when the lefthand tube 10 ,is conducting, the trigger circuit issaid to represent a binary '0 and when the right hand tube 11 isconducting, the trigger circuit is said to represent a binary 1.Accordingly, the lefthand tube loiis-hereinafter' designated 7 reset"when the *0 side is conducting; the righthand tube 11 is hereinafterdesignated the 1 side,- and the trigger is said to he set when the 1side is conducting. k

The anode of. the 0 side of the trigger is connected by a lead 12, ajunction 14, a resistor 16, and a lead 18 to a terminal +B which is' asource of positive potential. Similarly, theanode'of the 1 s'id'e of therigger is con nected by alead {13, a junction 15, a resistor 17, and. a

lead 19 to terminal -|-'B.- The cathodes of both sides are connected bya common cathodelead 20 to ground.- K

flihe grid of the 0 side, hereinafter designated the 0 grid, isconnected-through a junc'tion22 and a resistor 24 to a terminal -C whichis a source of: negative po tential. The grid of thel side, hereinafterdesignated the 1 grid, issimilarly connected. through a junction 23 anda resistor 25 to the terminal -C. The 0 grid is also connected throughjunction 22, a 're'si's'tor 30 in parallel with; a capacitor 32,junction 15, and lead 13, to the l anode. The l grid issimilarlyconnected'through junction 23, junction 14, and lead 12 to the0 anode,

A set input terminal 41 is connected through a capacitor 43, a diode45,.a1 junction 36, alead 34 and junction'22 to the 0 minal 40 isconnected througha capacitor 42, a diode 44,. a junction 37, a lead 35fand junction 2-3 to' the 1 states of the circuit in terms of binary aresistor 31 in parallel with a capacitor 33,

grid.- Likewise, a; reset inputter,-

grid. A symmetrical input terminal 46 is connected to both the ()and 1grids and through a capacitor 47, a pair of diodes 49 and 48, junctions36 and 37, and junctions 22 and 23, respectively. r

f If a negative pulse is applied to the symmetrical input terminal 46,it causes the circuit to trigger from one state of equilibrium to theother. Assuming that the side is initially conducting, a negative pulseapplied to terminal 46 is transmitted through diode 48 to the 1 grid,but since the 1 side is already cut off, the pulse has no eflect.However, the same negative pulse is transmitted through diode 49 to the0 grid causing a decrease in the potential at the 0 grid, and therebycausing the conduction of the 0 side to decrease. Consequently, thepotential at junction 14 rises, and this rise in potential is coupled bycapacitor 33 and resistor 31 to the 1 grid to initiate conduction in thea 1 side. The conduction of the 1 side lowers the potential at junction.15. This fall in potential is coupled by capacitor 32 and resistor 30 tothe 0 grid, thereby lowering the 0 grid potential and further reducingthe conduction of the 0 side. Conduction increases in the 1 side anddecreases in the 0 side until a state of equilibrium is reached with the1 side fully condcting and the 0 side cut-off. Each subsequent negativepulse applied to terminal 46 similarly reverses conduction from one sideto the other. A negative pulse applied to the set terminal 41 sets thetrigger to -1 if it is conducting on the 0 side, but has no effect onthe trigger if it is already set to 1. Assuming once again that thetrigger is conducting on the 0 side, a negative pulse applied toterminal 41 is coupled by capacitor 43, diode 45, and lead 34'to the 0grid. Diode 49'blocks this pulse from the 1 grid. The negative pulse onthe 0 grid causes conduction to reverse from the 0 side to the 1 side inthe manner hereinbefore described. Similarly, a negative pulse appliedto the reset terminal 40, resets the trigger to 0 if the trigger isconducting on the 1 side, but has no effect on the trigger if it isalready reset to O. i As previously mentioned, the trigger circuit isadapted to control other devices, such as a gating circuit, by thechanging potential levels at junctions 14 and 15. When i the triggerstands reset to 0, the potential at junction 15 is relatively high, andthe potential at junction 14 is relatively low; the converse is truewhen the trigger stands set to 1. These potentials are available at apair of control ouptut terminals 38 and 39, which are connected tojunctions 15 and 14, respectively. 7

A block representation of trigger circuit T is shown in Fig. 2 as arectangle. The symmetrical input terminal 46 is at the bottom center ofthe rectangle and the reset and set input terminals 40 and 41 are at thebottom left and bottom right of the rectangle, respectively. The controloutput terminals 38 and 39 are shown at the top left and top right ofthe rectangle, respectively.

While a vacuum tube type tri ger circuit has been shown, it should herealized that other'forms of trigger circuits may be employed. Forinstance,- a suitable modification of the ferro-resonant triggercircuit, described in Automatic Digital Calculators by Booth and Booth,pub

lished by Butterworths Scientific Publications, London,

could be used without departing from the spirit of this invention.

' Gate I A second element employed in the present invention is a gate,anexample of which is the well-known pentode gate shown as G in Fig. 3.Gate G comprises a pentode vacuum tube 50 which-is normally biased wellbelow cut off by a source of bias potential Cl. i The bias of tube 50can be raised to slightly below cut 01? by the application of arelatively high potential to an arming terminal 51 which is connected tothe suppressor grid of the tube. The gate-output is through atransformer 53. The primary winding of the transformeris in the anodecircuit of tube 50, and the secondary winding is connected to a pair ofoutput terminals 54.

. When a relatively low potential is present at the arming terminal 51,the tube remains biased well below cut off; thus, the gate is said to beclosed, because an interrogating pulse applied to the control grid atterminal 52 produces no output at terminals 54. However, in the eventthat a, relatively high potential is present at the arming terminal 51,the bias of tube 50 is slightly below cut 01f; thus, the gate is said tobearmed, because, if a .positive interrogating pulse is applied to thecontrol grid at terminal 52, tube 50 will conduct and produce an outputsignal at terminals 54. By proper choice of connection, either positiveor negative output pulses may be obtained from the secondary of theoutput transformer 53 at terminals 54. i

In Fig. 2 a gate G is shown as a circle having within it a smallercircle connected to the control output terminal 39 0f trigger circuit T.This represents a typical arming connection from a trigger circuit andindicates that gate G is armed when and only when trigger circuit Tstands set to 1.

Fig. 4 illustrates one modification of the gate shown in Fig. 3. Themodification consists of the addition of a resistor 55 connected betweenthe suppressor grid of tube 5 0 and a low-potential source B. Thus inthe absence of any connection to the arming terminal 51, i.e'., if aconnection to the arming terminal is opencircuited, the suppressor gridassumes a low potential and efiectively closes the gate. Thischaracteristic of the modified gate permits the use of a simplifiedcontrol unit as described hereinafter.

Although pentode vacuum tube gates have been shown, other types of gatesmay be used, for instance suitable versions of the diode gates orferromagnetic gates as described in Automatic Digital Calculators byBooth and Booth, supra.

Delay line A fourth element employed in the invention is a delay line, atypical example of which is shown schematically in Fig. 5 as adistributed parameter delay line of the type disclosed in Fig. 5 of US.Patent No. 2,467,857, issued April 19, 1949, to J. H. Rubel et al., towhich reference is made for a full description. Pulses impressed upon aninput terminal 70 of the delay line D are delayed a required intervaland appear at an output terminal 71. In Fig. 2 a delay line D is shownin block form as a small square.

Although a distributed parameter delay line is shown, other delay.circuits, such as well-known lumped parameter delay line, may beemployed. In fact, it is often possible to choose circuit components sothat necessary delay will result from the time constants'associated withthe circuit in which case a separate delay element is unnecessary.However, for clarity of explanation delay lines are shown in theaccompanying drawings wherever azdelay is necessary for the properoperation of the invention. 1

Recirculation memory A- fifth element employed in this invention is a recirculation memory of the type disclosed by White and Reinholtz in thepreviously mentioned copending application Serial No. 413,388, filedMarch 1, 1954. Briefly, a recirculation memory of this type comprises atrigger circuit which receives binary signals from a magnetic readingtransducer and transmits these signals to a mag fnetic writingtransducer where they are rewritten. To

a pair .of diodes 135 ,and136 to mutually isolate the illustrated 1nFig. 7, a recirculation memory as embodied in thepresent inventioncomprises a magnetic medium in the form of two diametrically positionedgroups 141 and 149 of magnetizable segments, herein? after calledislands? embedded along the periphery of a disc 140 which-is constructedpreferably of nonmagnetic material. A reading transducer :,80 includes acore 143 having a gap 144 disposed in cooperative relation with disc140. A winding 145 on core 143 is connected by a pair of leads 116.and126 to the 0 and 1 inputs, respectively, of a bistable circuit 150 whichmay be of the type shown in Fig. l. A writing transducer 83 includes acore 146 having a gap 147 disposed in cooperative relation with disc140. A center-tapped winding 148 on core 146 is connected by a pair ofleads 89 and 99 to the O and l outputs respectively, of the bistablecircuit 150.

Each magnetic island 141 or 149 may represent or store a binary digit.If an island is magnetized in a given direction it representsa binary 1;if magnetized in the opposite-direction it represents a binaryO. Thus,each group of magnetic islands 141 or 149 may represent or store abinary number or word, For simplicity of illustration, only six islandsare shown in each group, although it is to be u uderstood thatinpractice ajgreater number of islands may be used. For examplesatisfactory results have been attained using as many as thirty-fiveislands in-each group 'on ,adisc six inches in diameter. w

When a magnetic island is sensed or read by the reading transducer 80,whether the island is magnetized to represent a binary O or-a binary 1,the trigger circuit .150

assumes a corresponding state of operation-which causes the writingtransducer to rewrite the representation of the sensed binary digit asfully described in the above-mentioned application. Tranducers 80 and 83are normally disposed diametrically opposite each other relative to disc140; therefore, the 'value 0 to 1 that is read from an island in onegroup is written on the corresponding island of the other group. As disc140, rotates all of the digits of a word contained in one group ofislands are sequentially read by the reading transducer 80 and throughthe action oftrigger circuitlSt). are rewritten by the writingtransducer 83 into'the corresponding islands of therdiametricallydisposed group. Thus, each group 141 and 149 normally contains the samebinary word,

and this word is continually recirculated from one group to the other.

New information can be entered'into the recirculation memory through aninput terminal 131 to the 'Qside or through, aninput terminal 132 to thelfsidd'bftrig'ger circuit 150. A positive input pulse 'a'pplied'toterminal 131 causes the 0 side to conduct; hence, a representation of 0is written into an island of disc 140 by transducer 83. Similarly, apositive pulse applied to terminal 132 causes the l side of triggercircuit 150 as; conduct, and a representation of a 1 to'be-w'ritten intoan island :of'disc i (Fig. 7).

,connefificd to-an arming terminal :of aygate. A gate thus is conductingon the 0 side.

Time intervals H As an aid in explaining the operation of an arithmeticorgan comprising several recirculation memory units, certainztimeintervals associated with the rotation of each memory disc will bedefined.- 1

The time interval of rotation between successive magnetic islands isrepresented by "an arc DI on the disc 140 This time interval .iscalled adigit interval? since during this interval one digit is, read by thereading transducer and is then rewritten by the writing transducer.

The time interval required for the transferof a word from one group ofislands to the other groupofrislands is designated a word interval. Thisinterval is represented by arcs WI and is substantially the sum of thedigit intervals of a group of magnetic islands.

A. certain time intervalis reserved for the purpose of i co-ordinating amemory unit with other units of a computer, For instance, inter-registertransfer can be effected, or synchronizing signals can be transmittedduring this interval. Thistime interval is designated a control intervaland 'isrepresented by arcs CI of disc 140. A

. control interval occurs between each two word intervals; thus therea-re two control intervals during each rotation of any memory disc.

ARITHMETIC UNIT I General description 'The arithmetic unit embodying thepresent invention includes three recirculation'memories which may be ofa the general type] shown in Figs. 6-8, and which are identifiedhereinafter as the accumulator memory,.the entry memory, and themultiplier memory. Augends and minuends are entered into the accumulatormemory;

addends, subtrahends and multiplicands are entered into theent'rymemory;and multipliers are entered into the multiplier memory. After entry oftwo operands into the appropriate memories, the desired type ofarithmetic operation is selected and the selected operation is theninitiated. i

During addition or subtraction, the accumulator memcry and entry memorycooperate with a timing .'circuit, a

carry circuit, and a control circuit for additively or Suhtractivelycombining operands, and each sum or difference is stored in theacciunulator memory. During multiplication, the entry and multipliermemories cooperate with the timing, carry and control circuits to formsuccessive partial products of operands, and the partial prod.-

140. Asymmetrical input terminal 130 is also provided. I

' A negative input pulse applied to terminal 130 causes trigger circuit150 to change from one state of conduction to thevother. The pulsesapplied to the input terminals must, of course, be of sufiicientmagnitude to override the signals irom thereading transducer, Anyconvenient timing method that is appropriate to synch'onizethe inputpulses with the rotation of the memory disc may. be

provided along with a suitablesentryregister. Since they form no part ofthe present invention they are notshown in the accompanying drawings. 3

A block representation of a recirculationmemory M is shown in Fig.- 6.Terminals 13 1 and 13 -2 are the reset 'memo 55 ry nets are accumulatednd stored in the accumulator During the'firstIwordinterval followinginitiation of addition or subtraction, the successively higher .orderdigits of one operand are combined with ordinally-corresponding digitsofthe other operand. Each additive or subtractive combination of apair ofordinally corresponding digits occurs during a single digit interval,and any stored carry from a previous order 'iscombined with the twooperandv digits during the same digit interval. The three possibledigits that may. be combinedduring a digit interval, i.el, two'operanddigits and a carry-digit,

are; accumulated serially during the digit interval. First,

thfe'augend or minuend digit is; registered; then a carry digit, if; oneexists, is combined therewith to form a partial sum or difference;finally, the addend or subtrahenddig-it is combined with the partialsumfl or diiferenceto produce a total ordinal sum or difference, andanynew carry digit is stored.

-The' addition or subtraction operation continues '"throughoutanumberof' digitintervals equal to the hum her of orders in' a'word'that can be stored in a recirculation memory. The present invention isillustrated by a memory disc 140 (Fig. 7), comprises six islands,although it will be obvious that the invention is not limited to thissmall number of orders.

Since the accumulator memory is adapted to store only a six-order wordin the illustrated embodiment, multiplication is confined to a six-orderproduct; therefore, the illustrated multiplication circuit is adapted tocombine two three-order factors. The multiplicand word is entered intothe three highest orders of the entry memory and the multiplier word isentered into the three lowest orders of the multiplier memory. Duringthe first word interval following initiation of multiplication, thelowest-order digit of the multiplier is sensed, and if it is a 1, itcauses entry of the entire multiplicand word into the accumulator memoryto form a first partial product. If the lowestorder multiplier digit isa 0, the multiplicand is not entered, and the first partial productcomprises all Os. During multiplication, each word that is written intothe accumulator or multiplier memories is shifted one order to theright, as written in ordinary notation. In the absence of this shiftingoperation, the first partial product would be entered into the threehighest orders of the accumulator memory, because the multiplicand isstored in the three highest orders of the entry memory, as previouslymentioned. However, the shifting operation causes this partial productto be entered into the second-, third and fourth-highest orders of theaccumulator 'memmy in preparation for combining it with a next partialproduct in proper ordinal alignment.

The right-shifting of the multiplier causes the lowestorder multiplierdigit to be lost, and the second-lowestorder multiplierv digit to besensed during the second word interval for controlling entry ornon-entry of the multiplicand into the accumulator memory as a secondpartial product, where it is combined with the shifted first partialproduct. The above process occurs during eachof three consecutive wordintervals, after which the multiplication is completed and the totalproduct is stored .in the accumulator memory.

Recirculation memories Referring to Fig. 9, the accumulator, entry andmultiplier memories are designated Ma, Me, and Mr, respectively. MemoryMe is of the type shown in Figs. 6-8, while memories Ma and Mr are ofthat same general type with amodification which is provided tofacilitate a single order of right shift during the transfer of a wordfrom one group of islands to another on the same disc during each wordinterval of multiplication.

Each memory Ma and Mr is provided with an additional writing transducer85 (identified with the accumulator or multiplier memory by the sufiix aor r, respectively), hereinafter designated a shifting transducer, whichisdisposed in cooperative relation with the corresponding memory disc140, but advanced from the normal writing transducer 83 by one digitinterval of arc in the direction of rotation of the disc. If trans ducer83 is enabled and transducer 85 is disabled, a word that is stored onthe disc is recirculated in unchanging ordinal position. On the otherhand, if transducers 83 is disabled and transducer 85 is enabled, thestored word .is shifted one order to the right each time it is read andrewritten.

Each transducer 83 or 85 isselectively enabled by con- ,memory Ma and aswitch S4 in memory Mr. The operations of switches S2 and S4 are alike,and only the forme will be described. 7 7

Switch S2 is a three-position switch, having an 0115" position, anAdd-Subtract position, and; a Multiply position. In its Off andAdd-Subtract positions, switch S2 applies +B power to the writingtransducer 83a directly through a lead 154a, and a recirculating word isnot shifted. When switch S2 is in its"Multiply position, it applies +Bpower to the writing transducer 83a until multiplication is initiated;then it applies +B power to the shifting transducer a until themultiplication is completed. +B is connected through a lead 157a to abrush 156a which normally rests on a conducting segment 189a of acontrol disc C1. Disc C1 is keyed to a normally motionless shaft 180 andis rotated when shaft 180 is rotated, as hereinafter described. Whendisc 01 is at rest, a circuit is completed from brush 156a throughsegment 189a, a conducting ring 196a that is electrically connected tosegment 189a, a brush 151a that rides on ring 196a, a lead 158a and lead154a to apply +B power to transducer 83a when the foregoing circuit iscompleted, a recirculating word is not shifted.

When switch S2 is set to its Multiply position, +B is also connectedthrough a lead 159a to a brush 153a that rides on a conducting ring197a. The latter ring is secured to a control disc C2 which is alsokeyed to shaft 180 for rotation therewith. Ring 197a is electricallyconnected to a conducting segment 199a of disc C2, segment 1990 beingnormally disconnected from a brush 152a which normally rests on aninsulating segment 198a of the disc C2. Brush 152a is connected by alead a to the center tap of the coil of the shifting trans ducer 85a..

When shaft is rotated, as hereinafter described, brush 156a. contacts aninsulating segment 188a of disc C1, thereby disconnecting +B from thewriting transducer 83a, and brush 152a, at substantially the sameinstant, contacts the conducting segment 199a, thereby applying +B powerto the shifting transducer 85a. During the rotation of shaft 180 and itsdiscs C1 and C2, therefore, the shifting transducer is enabled and thewriting transducer 83a is disabled, and the stored word is shifted'oneorder to the right each time it is read and rewritten. It is to be notedthat a pair of .diodes are placed in series with each writing transducer83 and 85. These diodes serve to decouple the writing transducers fromone another for otherwise the unenergized half of the selectedtransducer and both halves of the unselected transducer in series wouldform a parallel circuit with the energized half of the selected writingtransducer.

It will be seen that +B power is not applied to shifting transducer 85aduring addition or subtraction, when switch S2 is in its Add-Subtractposition, and that the disconnecting operation of disc C1 does notremove +B power from transducer 83a during addition or subtraction,because power is applied directly to that transducer throughthefAdd-Subtract terminal of switch S2.

Memory discs 140a, 140e, and 140r are all keyed to a constantly rotatingshaft 142 for rotation therewith, and their groups of islands are soaligned with respect to their associated transducers that each wordinterval of one memory is substantially concurrent with a word intervalof the other two memories; similarly, control intervals aresubstantially concurrent throughout the three memories.

The drive mechanism for shaft 180 operates'in such manner that rotationof that shaft, and of control discs C1 and C2 begins during a controlinterval, as hereinafter described. Shaft 180 is driven through onecomplete rotation and then stopped. The gear ratios for driving shafts142 and 180 are such that shaft 142 makes one and one half rotations foreach complete rotation of shaft 180; therefore, a rotation of shaft 180embraces three control intervals and three word intervals, beginning andending within a control interval. Thethree word intervals are providedfor a complete multiplication operation in the three-order system hereinillusshould be" modified by providing only one tooth 183 on its ratchet,thereby permitting the clutch to engage'o-nly.

assess? 10- the clutch. The clutch disclosed in the Avery patent readingtransducer 80a, a I V scribed;'if the oridinal. augend digit is a 0,tr1gger 50a 10 in the manner hereinbefore deis reset to through itsreset input, and if the digitfis a 1, trigger 150a is set to 1 throughits set input. Following entry ofthe augend digit, any stored'carrydigit of 1 is entered intothesymmetrical input of trigger 150a, therebyreversing the state of that trigger to'represent an increase of unity inthe value represented by the state of "trigger 150a. The following meansare provided for entering a stored carry digit of 1 into trigger 150a.

A" clock pulse generator 208 is illustrated in Fig.9 as comprising anonmagnetic disc 209 that is keyed to the memory-disc shaft 142 forcontinuous rotation therewith.

when its ratchet is in full cyclic position .(during a controlinterval). Clutch 181 is engaged by depressing a key 182 whichhas an arm191 with a yieldable tip, 192

overlying an ear 193 on a bellcrank 185. Depression of key 182rocksbellcrank 185 clockwise about afi xed shaft 186 for moving a pawlend 187 of the bell crank to its clutch-engaging position. Bellcrank 185is spring urged counter-clockwise to restore pawl 187 to itsclutchdisengaging position, but can do so only after the clutch hasdriven shaft 180 through one complete rotation. 7

Key 182 is also spring urged to its upward position. During thedepression of this .key, the yieldable tip 192 in its arms 191 releasesear 193 on 'bellcrank185 when the bellcrank engages a stop member 1194;therefore, pawl 187 disengages clutch v181 after one rotation of shaft180, even if key 182 remains depressed for more than one rntat-ion ofthat shaft. Key' 182 shouldbe fully de- "pressed against a stop member19510 insure the release of the b'ellcrank ear 193 by tip 192 of arm 191on the key. 1

Switch S4 cooperates with a pair of control discs C5 and C6, which arekeyed to shaft 180 for rotation there: with, to apply +B power totransducers 83r and 85r of the multiplier memory. The operation ofswitch S4 and its related circuitry is the same as thepreviously-described operation of switch S2 and its related circuitryin'the accumulator memory.v Therefore, during multiplication,

the multiplier word standing in memory Mr is shifted one order to theright during each word interval, along with the accumulated partialproduct in memory Ma.

Addition It is recalled that in addition operations the accumulatormemory Ma additively, combines two operand digits and-a carry digitduring eachdigit intervaliof a single word interval. The following tableillustrates the eight possible combinations of digits that can be addedduring a digit interval: 1 1 a r v1 vrr VIII 7 I II III V v Carry 0 0' 00 1 1 1 l Augend 0 1 0 '1 o 1 0 1 Addend 0 p O 1 1 0 0 1 1 Sum 00" 01 0110 01' 1o 10 I .11

. The memory trigger 150a receives representations of the three digits,seriatim, during each digit interval, as hereinafter described, and itsfinal state at the end of the digit interval represents the lower-orderdigit of the binary of the three, digits, as shown in the foregoingtable.

""A carry trigger T1 cooperates with memory Ma to store any carry digitof l'that occursv during a digit interval,'i.e., the state of trigger T1at the end of a-digit' interval represents, the higher-order digit ofthesum-of the three additively combined digits. Iftrigger T1 stands at0, it represents a carry digit of 0 (generally designated as the absenceof a carry digit); if trigger T1 stands at '1, itrepresents the presenceof a stored carry digit of. 1. Trigger T1 also controlsentry of anystored carry digit into memory Ma during thenext consecutive digitinterval. v 1

During a'digitinterval, the augend digit is first entered into memorytrigger. 150a from disc 140a through a Two groups of permanentlymagnetized islands 210 are embedded in theperiphery of disc 209 andcooperate with a reading transducer,-shown schematically at 211 forgenerating a clock pulse each time an, island 210 rotates pasttransducer 211. In the illustrated arithmetic unit,

there are six islands 210 in each group, corresponding to the sixislands 141 and 149 (Fig. 7) in each group on a memory disc 140. Theislands 210 (Fig. 9) are so arranged relative to shaft 142 andmemorydiscs 1 4021, 140a and 1407 that a clock pulse is generatedsubstantially at the beginning of each digit interval during each wordinterval, and no clock pulses are generated during any control interval.I a

The output of transducer 211 is connectedby a lead 212 to the input of acarry sensing gate Gl that is armed be explained hereinafter.

stored carry digit of l.

by the 1 side of the carry trigger T1. The output of gate G1 isconnectedby a pair of 1eads213 and 215 to the reset input of trigger T1. Eachclock pulse interrogates gate G1 to sense for a carry digit of 1. Ifsuch a carry digit is stored in trigger T1, gate G1 is armed,-and theclock pulse is transmitted through gate G1 and leads 213 and 215- toreset trigger T1 to 0, .thereby'cancelling the The'output of gate G1also is connectedthrough lead 213, a delay line D1, a lead 217, a lead221; a lead 223, a delay line D3, and a lead 224, to the symmetricalinput of the accumulator memory trigger 150a for reversing the stateofthat trigger in response to the sensing of a carry "digit of l. atgate'G1. Delay line D1 is provided for delaying entry of the carry digitinto trigger 150a until after the augend digit has been entered fromdisc a in the manner previously described. Delay line D3 further delayscarry entry, but has an additional purpose that will The output of delayline D1 also is connected through lead 217 to the input of a carrycontrol gate G2 that is armed, during addition, by the 1 side of theaccumulator memory trigger a through a control lead 230, a switch S1 anda control lead 216. Switch S1 is a three-position switch'that is set toan'fAdd-Multiply position prior to the initiation of an additionoperation. The output of gate G2 is connected by a lead 219 to eitherthe set .or

the symmetrical. input of carry trigger T1. If trigger 150a standsat 1when gate G2 is interrogated by the output' pulse from delay line D1(representing a sensed carry digit of 1 in trigger T1), this indicatesthat the augend digitwas a 1 and that, combined with the carry digit ofI -1, it will form abinary sum of 10, and a new carry must be stored.Therefore, if. gate G2 is armed it transmits the interrogating pulsefrom delay line -D1 to either the set or symmetrical input of triggerT1, thereby setting that trigger back to l for storing a new carry digitof 1.

It will be noted that delay line D1 permits trigger T1 to be fully setto 0 through lead 215 before the set pulse is applied through lead 219.Delay line D1 also permits trigger 150a to be fully set, tol by theaugend digit for arming gate G2 before the carry pulse is applied togate G2. Delayv line-D3 further delays entry of the carry digit, therebyinsuring that the condition of gate G2, 'at' 'thetime it isinterrogated, is determined entirely by. the augend digit, i.e., thatthe carry digit hasnot been entered into trigger 15011 at this time.

, l1 After a carry digit of 1, if such occurs, has been entered into theaccumulator trigger 150a, the corresponding ordinal addend digit isentered into that trigger under joint control ,of the entry memory Meand the clock pulse generator 208. An addend digit of 1.is representedby a pulse applied to the symmetrical input of trigger 150a, and anaddenddigit of is represented by the absence of an input to thattrigger.

Each ordinal clock pulse that is generated by clock described. Theoutput of gate G3 is connected to the input of an addend-multiplicandgate G4 that is armed by the 1 side of the entry memory trigger 150a.The output of gate G4 is connected through the previously described lead223, delay line D3, and lead 224 to the symmetrical input of theaccumulator trigger lStia.

It is recalled that an input pulse to trigger ila representing a carrydigit of 1 is transmitted through delay lines D1 and D3 in series.Similarly, an input pulse to trigger 150a representing an addend digitof 1 is transmitted through delay lines D2 and D3 in series. In order tocause any addend digit of 1 to be entered into trigger 150a after entryof any stored carry digit of 1, delay line D2 has a characteristic delaytime greater than that of delay line D1. Thus, after entry of the augendand carry digits, any addend digit of 1, represented by a pulse fromclock pulse generator 268 transmitted through leads 212 and 225, delayline D2, gate G3, gate G4 (which is armed by trigger 150s if and only ifthe ordinal addend digit is a 1), lead 223, delay line D3, the lead 224,is entered intorthe symmetrical input of trigger 15th:, therebyreversing the state of that trigger to represent an increase of l in theordinal sum.

The output of gate G4 is connected not only to the input of delay lineD3, but also is connected by leads 223, 221, and 217 to the input of thecarry control gate G2 which, it is recalled, is armed by the 1 side oftrigger "I'Stla during addition. The output pulse from gate G4, whichrepresents an addend digit of 1, is therefore transmitted through leads223, 221, and 217, gate G2 and lead 219 for storing a carry in triggerT1 if trigger 150a stands at 1. It will be seen that trigger 150a standsat 1,

and gate G2 is armed when it is interrogated by a 1-addend pulse fromgate G4, if either the augend digit or the carry digit was a 1. In suchcase,-the further addend digit of 1 produces the binary sum 10, whichrequires that a carry be stored for entry into the next higher order. Ifneither the augend nor the carry digit was a 1,

:trigger 159a stands at O, gate G2 is closed, and no further carry digitis stored in trigger T1. If both the augend andcarry digits were ls, acarry digit was already stored by a pulse transmitted from delay line D1through gate G2 in the manner hereinbefore described; in this case,trigger 150a stands at 0, representing the lower-order digit of thepartial binary sum 10, gate G2 is closed, and no further carry storagepulse is transmitted through lead 219 to trigger T1.

The presence of delay line D3 between lead 224 and the junction'of leads223 and 221 delays entry of a l-addend pulse into trigger 150a untilgate G2 is sensed; therefore, the condition of gate G2, when it issensed by a l-adde-nd pulse, is determined exclusively by the combinedvalues of the augend and carry digits. For this purpose, delay line D3may be eliminated if the inherent switching time of trigger 150a issufficiently long to permit gate G2 to be sensed by a l-addend pulsebefore trigger 150a is reversed by the same pulse to thereby reverse thecondi- .tion of gate G2.

The previously-mentioned multiplier gate G3, through which each clockpulse must pass before interrogating the addend-multiplicand gate G4, isarmed, during addition,

12 through a control lead 204, a three-position switch S3 that is set toan Add-Subtract position for addition, a control lead 222, and a brush161 that rides on a conducting ring 162. Ring 162 is secured to acontrol disc C3 that is keyed to the previously-described shaft forrotation therewith. Disc C3 comprises a single conducting segment :163and an insulating segment 165. The conducting segment 163 subtencls anangle corresponding to one word interval. A brush 164 rides on theperiphery of disc C3, and is connected to'a source +C of gate-armingpotentialr When brush 1'64 engages conducting segment 163, +C potentialis applied to the arming input of gate G3 through the circuitdescribedabove,

including switch S3. When clutch 181 stands disengaged, i.e., in itsnormal, or rest condition, control disc C3 is in such position thatbrush 164 rests upon insulating segment 165 and gate G3 is closed.Therefore, clock pulses from the continuously-rotating disc 209 arenormally blocked by gate G3. When addition is initiated by engagingclutch 181 during a control interval, as hereinbefore described, controldisc C3 rotates to bring conducting segment 163 under brush 164approximately at the beginning of the next word interval, and brush 164remains in contact with segment 163 during and only during that wordinterval; therefore the gate-arming potential +C is applied to gate G3for arming that gate during the first word interval following theinitiation of addition.

Due to the requirements of a multiplication operation, hereinafterdescribed, three word intervals (and three control intervals) occurwhile shaft 18%) makes one complete rotation under the control ofclutch'18'1. Since only one word interval is required for addition orsubtraction, the two final word intervals, as well as two controlintervals of an addition or subtraction operation are idle. It will beobvious that a separate one-cycle clutch could be provided to turn acontrol disc such as C3 during only one word interval (and acorresponding control interval)., However, the rotation of shaft can bequite rapid, and the cost of an extra clutch would be greater, for mostpurposes, than the cost in time of permitting two idle word intervalsand two idle control intervals to occur during addition or subtraction.

The need for closing gate G3 at all times except during an arithmeticoperation can be eliminated by keying two clock pulse generator discs,similar to disc 209, to shaft 18d instead of to the constantly-rotatingshaft 142. In such case, one generator would be selected, by a switchsimilar to switch S2, for operation during addition and subtraction, andwould have only one series of islands corresponding to the single wordinterval of addition or subtraction. The second generator would beselected for operation during multiplication, and would have a series ofislands corresponding to each word interval of multiplication. With thisarrangement, clock pulses are generated only during rotation of shaft1180, and need not be blocked at other times. However, it should benoted that for an accumulator having n orders, the multiplication clockpulse disc on shaft 180 would need a series of 11 islands in each of nword interval segments, the latter being separated from each other by n"control interval segments. For the six-order accumulator illustrated,such a clock pulse generator would be entirely practical, but for atwenty-order accumulator, as pro vided on many calculating machines, 2020=400 islands 'would have to be compressed into half the periphery of adisc (there are no islands in the control interval segments). Theequivalent of this arrangement may be achieved by the use of acontinuous medium rather than Y interval of the single word interval ofaddition, the appropriate' set of ordinally-corresponding -augend, carryand addend digits are added, in the sequence named, by

first setting the accumulator trigger 150a to a condition representingthe value of the augend digit, and then reversing the state of thattrigger in response to the occurrence of each digit 1in'thec'orresponding order of the carry and the addend. A carry digit of1 from the next lower order is stored in trigger T1g This carry digit,is sensed at' gate G1 by an ordinallyrcorresponding clock pulse fromclock pulse generator 203, and is then en tered intotrigg'er 150a. Thesensing of a stored carry causes that carr'y'to be cancelled. An addenddigit of l is sensed at gate G4 which is controlled by the correspondingorder of the'entry memory Me, and is then entered into trigger 150a. Anycombination of two ordinally corresponding digits 1 is sensed at gate G2and causes, .a new carry digit of 1 to bestored in trigger T1 for entryinto the next higher order of the accumulator memory Ma. As each ordinalsum digit is formed in a Each digit that is recorded'onan island of theaccumulator memory during. multiplication is written by the shiftingtransducrBSa. Therefore, the digits of the multiplicand word, or aseries of three' Os, depending on thevalue 0f the lowest-ordermultiplier 'digit, are

, written in the" 'second-, thirdand. fourth-highest-order islands ondisc 140a during the first word interval, there the multiplier word oneorder to the right during each 7,

word interval. Thus, both the partial product and multiplier words areshifted one order to the right" during each word interval, andsuccessively higher-order multi- Each ordinal multiplication process 1splier digits control entry on non-entry of the multiplicand into memoryMa during successive wordintervals; each new entry is combined withtheishifted andaccumulated previous entries to form, a new partialproduc't. At the end of the third word interval, in the illustratedembodi merit of the invention, the total product of six orders stands inthe accumulator memory Ma. j

' performed by the operation of the clock pulse generator 208 incooptrigger 150a, it'i's recorded in memory disc 140a, which thereforecontains the entire sum at the end of one word' interval. At this timethe carry and addend entry circuits are disabled and the sum isrecirculated in memory lVla' for readout, or for use as aifurthe'roperand.

Subtraction A into memory Ma and the subtrahend into memory Me.Subtraction is performed in the illustrated machine exactly as additionis performed, except that switch S1 is set to a jSubtract position priortoinitiating the operation. With switch S1 .inits 'Subtract position,the carry control gate G2 is'armed by the 0 side of trigger150ai'through a control lead 231, switch S1, and control lead 216. Withthisarming circuit completed, gate Y In preparing for subtraction, theminuend' is entered eration with the previously-described carrycircuitry, the multiplier ga-te G, the addend-multiplicand gate G4, andthe accumulator trigger 150a. During each .wor d interval ofmultiplication, six clock pulses are applied in se quence to the inputof gate G3, which is armed through out that word interval if and only ifthe corresponding digit of the multiplier word is a 1. The means forarm'- ing gate G3 during multiplication will be described hereinafter.Assuming forthe present that gate G3 is armed,

thereby indicating that the -multiplican'd Word is to. be 1 entered intomemory Ma as a partial product during the current word interval, all sixclock, pulses that occur during the word interval are transmittedthrough gate G3 to the inputof gate G4. 'The latter gate is'cont'rolledby the 1' side of trigger 150e, 'as previously described;

therefore, it produces an input pulse during each digit interval inwhich a multiplicand digit of '1 is read'by transducer 89c, and thisoutput pulse is transmitted to the symmetrical input of trigger 150a totherein be additively combined with the ordinally-corresponding digit ofany, previously-accumulated partial product. If gate G3 minu'end by theprocess hereinbefore described, except that'a carry is stored, duringsubtraction, when a digit -l is combined with a 0. At the end of theword interval, the difference word stands in memory Ma, and isthereafter recirculated for readout or for use as a subsequent operand.p Y Multiplication In preparation for multiplyingin the presentfmachinethe multiplicand' word is entered into the three highest orders ofmemory Me and the multiplier word isentered' into the three lowestorders of memory Mr. Also, switch S1 is set to its Add-Multiplyposition, and switches 52-84, which may conveniently be gauged, are setto their respectiveTMultiply positions: Multiplication is v 182 toengage clutch 181 for rotating shaft 180. 1

then initiated by depressing key The multiplication operation continuesthroughout a plier orders, i.e., three word intervals the illustratedembodiment .ofthe invention. interval, the lowest-order. digit of themultiplier is sensed; if thisdigit is a l, the entire multiplicandword'is' entered into the accumulator memory Ma as a first partialproduct during the firstthreedigit intervals of that word interval. 'Ifthe lowest-order multiplier digit is a 0,:a:0 is effectively enteredinto memory Ma during each of the, first threedigit intervals. a e

number of word intervals equal to thenumber of multi-- During thefirst.word rotationftherewith.

"Disc C4 is provided with a plurality of conducting is closed (becauseof a 0' multiplier digit), no clock pulses are applied to gate G4, and apartial product of all Os is entered into memory Ma during the currentword interval i Prior 'to th'e initiation of multiplication, switch S1is set to its Add-Multiply position, thereby controlling gate G1 fromthe 1 side of trigger a for producing additive carries. Thus, carrieswhich result' 'from the addition of previously-accumulated partialproducts and a currently-enteredpartial'product are sensed, added andstored in the manner previously described'in relation (0 4116 additionoperation. 'In multiplication, an output pulse from fgate G4, forsensing the carry control gate G2, represents a 'partial-product digitrather than an' addend digit, but the carry operations are neverthelessthe same" as those previously described.

Themultipliergate G3 is armed through control lead 204, switch S3 whichis set to its Multiply position prior to the initiation ofmultiplication, a control lead 241 and a brush 171' that rides, on aconducting ring. -172.' a The latter ringiss'ecuredt'o,the'previously-mentioned control disc C4, whichisikeyed toshaft *for segments 173 that are evenly spaced by an equal number ofinsulating segments'175. The number of conducting segmentscorrespondsto} the number of word intervals of amultiplicationoperation,'jwhich; in turn, corresponds to the number oforders in the multiplier were. I the illustratedembodiment of theinvention, the three-order mu tiplier word eq ire t t el e b th e ndu ngSegments 173 (and three insulating segments 175). A brush 174 rides onthe periphery of disc 04 and rests on an insulating segment 175 whenshaft 180* is stopped, i.e., when clutch 1S1 stands disengaged. Whenclutch 181 is engaged to initiate multiplication, disc C4 rotates tobring a conducting segment 173 into contact with brush 174 atsubstantially the beginning of the next word interval. The positions ofsegments 173 and 175 relative to brush 174, and the angles subtended bythese segments are such that brush 174 contacts a conducting segment 173during and only during each of the three word intervals ofmultiplication.

Brush 174 is connected by a control lead 252 to the 1 side controloutput terminal of a multiplier storage trigger T2. The latter triggeris adapted to be reset to 0, as hereinafter described, during eachcontrol interval, and to be set,to 1 just prior to the beginning of thenext word interval if and only if the lowest-order digit of themultiplier word in memory Mr is a 1. When trigger T2 is set to 1, itremains in that condition during the next word interval, and arms themultiplier gate G3 throughoutthat word interval, by means of theabovedescribed circuit including disc 04 and switch S3. If thelowest-order digit of the multiplier word is a 0, trigger T2 is merelyreset to O, gate G3 remains closed throughout the next word interval.The operation of gate G3 in performing ordinal multiplication operationshas been described previously. The following circuit is employed forcontrolling the state of trigger T2.

A control pulse generator 235 is employed for generating a control pulseduring each control interval. Generator 235 is illustrated in Fig. 9 ascomprising a nonmagnetic disc 236 keyed to the continuously-rotatingshaft 142 for rotation therewith. It is recalled that shaft 142 ,makesone complete rotation during each two word interval. Therefore, a pairof diametricallyopposed magnetic islands 237 are located on theperiphery of disc 236 and cooperate with a reading transducer showngenerally at 238 to generate an output pulse each time an island 237rotates past transducer 238. The positions of islands 237 relative totransducer 238 are such that a control pulse is generated during eachcontrol interval.

The output of transducer 238 is connected by a pair of leads 2'40 and242 to the reset input of trigger T2; therefore, each control pulseresets that trigger to 0. The output of transducer 238 also is connectedthrough lead 240, a delay line D4 and a lead 244 to the input of a gateG5 that is controlled, through a control lead 250, by the 1 side oftrigger 150r. The delay characteristic of delay line D4 is such thatgate G5 is interrogated by each control pulse after trigger 150r hasbeen set or reset by the lowest-order multiplier digit. If this digit isa 0, gate G5 is closed and trigger T2 remains reset to 0, therebycausing gate G3 to remain closed during the current word interval. Ifthe lowestorder multiplier digit is a l, gate G5 is armed when it isinterrogated by the control pulse, and trigger T2 is set to 1, therebyarming gate G3 during that word interval.

Since the multiplier Word is originally entered into the three lowestorders of memory Mr, and since the multiplier word in that memory isshifted one order'to the rightduring each word interval ofmultiplication, each successively higher-order multiplier digit becomesthe lowest-order multiplier digit in turrnand controls the state oftrigger T2 during'one word interval. After three word intervals ofmultiplication, the one-cycle clutch 181 automatically disengages andshaft 180 comes to rest. The total product stands in the six orders ofmemory Ma at this time, and continues to recirculate without furthershifting, for readout or for use as a subsequent operand.

I clairn:

l. In a recirculation memory, the combination of: a cyclically movingmagnetizable medium having successive areas thereon magnetized torepresent an ordinallyarranged binary word; a digit representing deviceadapted to assume either of two distinct states representative of thebinary digits 0 and 1 respectively, said device having a first terminalfor drawing current when said device is in its =1-representing state andhaving a second terminal for drawing a current when said device is inits O-representing state; a reading transducer adjacent said medium fordetecting seriatim the digits of said word; a passive connection fromthe reading transducer to said device for setting said device torepresent a detected digit; a first writing transducer adjacent saidmedium and spaced from said reading transducer by'a number of ordinalincrements at least equal to the number of digits of said word, saidfirst writing transducer having a centertapped winding and having theends of its winding connected through a passive circuit to said firstand second terminals; a second writing transducer adjacent said mediumand spaced from said first writing transducer by a predetermined numberof ordinal increments, said second writing transducer having acentertapped winding and having the ends of its winding connectedthrough a passive circuit to said first and second terminals; a powersource for said device; first and second cyclically operable powercontrol discs having complementary conducting and non-conductingsegments; means including said first disc for initially connecting saidpower source to the centertap of said first writing transducer; meansfor' driving said discs through single cycles of rotation; and meansincluding said second disc for connecting said power source to thecentertap of said second writing transducer for a predetermined intervalof each cycle.

2. In a circuit for serially combining first and second binary values; asource of clock pulses; an accumulating device operable to maintaineither of two stable conditions and having an input and a controlterminal; means for applying a pulse train representative of said firstbinary value to the input of said accumulating device; a carry storagedevice having an input and a control terminal; a first delay circuit; afirst gating means having an input connected to the pulse source andhaving an arming terminal connected to the control terminal of saidcarry storage device and an output connected to the input of said firstdelay circuit and to the input of said carry storage means; a secondgating means having an input connected to the output of said first delaycircuit and an output connected to the input of said carry storage meansand having an arming terminal; means connecting the control terminal ofsaid accumulating device to the arming terminal of said second gate forapplying an arming potential to said gate when said device is in apredetermined condition; a second delay circuit having an inputconnected to'said pulse source; third gating means having an inputconnected to the output of said second delay circuit; means connectingthe output of said third gating means to the input of said second gatingmeans; a third delay circuit having an input connected to the output ofsaid third gating means and having an output connected to the input ofsaid accumulating device; means connecting the output of said firstdelay circuit to the input of said third delay circuit; and controlmeans representing the serially occurring second binary value connectedfor control of said third gating means.

3.v In a binary multiplier, the combination of: a clock pulse source;first and second recirculation memories recirculating continuously andsynchronously with sald clock pulse source and each having an input andeach ncluding a continuously moving magnet c medium for storing binarywords, a digit representing device, a reading transducer adjacent saidmedium for detecting the drglts of a stored word and for entering adetected digit lnto said digit representing device, a normally operativefirst writing transducer energizable by said dev1ce forreplacing adetected digit in a normal writing location on said "17 medium, and anormally inoperativesecond writing transducer selectively energizable bysaid device for replacing a detected digit on said medium in a.right-shi-ftedrelation to the normal writing location; a thirdrecirculation memory recirculating continuously and synchronously withsaid clock pulse source and having an input and including a continuouslymoving magnetic medium for storing binary words, a digitrepresentingdevice, a reading transducer adjacent'the medium fordetecting the digits of a stored Word and for entering a detected digitinto said digit representing device, and a writing transducerenergizable by said device for replacing a detected digit in a normalwriting location on said medium; means for entering a plural ordermultiplier word into said second memory; means for entering a pluralorder multiplicand word into said third memory; gating means connectedto said clock pulse source and having first and second arming terminalsand having an output connected to the input of said first memory; meansfor selectively applying an arming potential to said first armingterminal of said gating means in accordance with a first predeterminedstate of the digit representing-device of said 'rd memory and forremoving the arming potential to said first arming terminal of said,gating means in accordance with a second predetermined state of thedigit representing device of said third memory; a manually-depressiblekey; means operable in response to the depression of said key andincluding a one cycle clutch for initiating a multiplication; meansoperable upon engagement of said clutch to disable the normallyoperative writing transducers of said first and second memories and tosubstantially simultaneously enable said normally inoperative writingtransducers of said first and second memories;

means including said first recirculation memory for -ac-- cumulatingsuccessive partial products; and multiplier storage means under controlof said second recirculation memory for selectively applying an armingpotential to said second arming terminal of said gating means torepresent a first predetermined value and for removing the armingpotential to represent a second predetermined value throughout eachsuccessive word period or a multiplication in accordance with eachcoiresponding successive digit of the multiplier word whereby saidgating means is jointly controlled by said multiplier storage means andsaid third recirculation memory for developing a pulse train at theinput memory representative of a partial product during each successiveword period ot a. multiplication.

4. In a calculating machine having first and second synchronizedmemories, the combination of: means for entering a plural-order firstoperand value into said first memory; means for entering a pluralcrdersecond operand valueintosaid second'memory; an accumulating devicecoupled to said first memory for cyclically receiving and retransmittingsaid first operand value and for receiving and accumulating said firstand second operand values; a continually operating clock pulse generatorhaving an output; gating means for connecting the output of said clockpulse generator to the input of said accumulating device and havingfirst and second arming terminals and enabled only by the conjointapplication of arming potentials to said first and second terminals;means including said second memory for applying an arming potential tosaid second terminal inaccordance with successive orders of said secondoperand value; a manually depressible key; a source of gate armingpotential; a normally inactive control disc including a conductingsegment; a vfirst brush for connecting said source to said segment; asecond brush for cyclically connecting said segment to said firstterminal upon actuation ott said disc; a normally disengaged clutcheffective upon being engaged to actuate said control disc for one cycleof op eration; and means operable in response to depression of said keyfor'engaging said Clutch. 1

wees-i p r 5. A multiplying device comprising: accumulating means foradding partial products including a first memory and an associated carrycircuit; asecond memory for receiving the multiplicand word;-a thirdmemory for re- 'ceiving the multiplier word; a clock pulse sourcesynchronized with the operation of said memories; gating meansconnecting said source to the input of said accumulating means andhaving first and second arming terminals; a connection from said secondmemory to said first arming terminal for applying an arming potential tosaid first arming terminal when said second memory is in a predeterminedstate of operation; a multiplier digit storage device controlled by saidthird memory for storing each successive multiplier digit throughouteach corresponding successive word period of a multiplication,operation; a normally open control connection from said 7 multiplierdigit storage device to said second arming terof said firstrecirculation minal of said gating means; a shaft; operation controlmeans in said control connection including a cyclically operablecommutator mounted on said shaft for completing said connectionthroughout each word period of a multiplication operation; a source ofpower; a cyclic clutch mounted on said shaft for connecting said shaftto said source of power; and means for releasing said clutch forinitiating a multication operation.

6. Ina circuit for ordinally combining binary values, the combinationof: a first recirculation memory comprising a moving magnetizable mediumhaving a first binary value stored thereon, a first bistable devicehaving a symmetrical inputand two asymmetrical inputs, a read ingtransducer passively connected to said asymmetrical inputs for settingsaid device to correspond to binary values represented on said medium,and a recording transducer passively connected to the output of saiddevice for recording on said medium values represented by said device;carry storage means under control of said first bistable device forassuming a predetermined condition to represent a stored value; a clockpulse sourcersynchronized with said memories; a first gating meanshaving an input connected to said pulse source and an output connectedto the symmetrical input of said first bistable device and controlled bysaid carry storage means to pass a pulse from said source to thesymmetrical input of said first bistable device when said carry storagemeans is in a condition to represent a carry value for setting saidfirst bistable device to represent the sum of said carry value and saidfirst operand value; a second recirculation memory including a movingmagnetizable medium having a second binary value stored thereon, and asecond bistable device for recirculating serially the second binaryvalue; a second gating means having an arming terminal and having aninput connected to said pulse source and an output connected to thesymmetrical input of said first bistable device; and means connectingthe output of said second bistable device to the arming terminal of saidsecond gating means for enabling said first gating means to pass a pulsefrom saidpulse source to the symmetrical input of said first bistabledevicewhen said second device is in a predetermined condition to setsaid first device to represent the sum of said first binary value, saidcarry" and said second binary value.

References Cited in the file of this patent UNITED STATES PATENTS;

(Other references on following page) 19 FOREIGN PATENTS Australia i)ec.9, 1955 Belgium Feb. 15, 1954 France Mar. 11, 1953 France July 7, 1954Great Britain Dec. 11, 1952 OTHER REFERENCES Thoresen: Design Featuresof a Magnetic Drum 20 Memory for the National Bureau of StandardsWestern Automatic Computer (SWAC). Proceedings of Electronic ComputerSymposium, April 20 to May 2, 1952, at Los Angeles. Pages II-O to II-9.Pages II-4 and 11-7 relied on November 1952 Richards: ArithmeticOperations in Digital Computers. Copyright 1955. D. Van Nostrand Co.Inc., pages 151-155.

